1. Technical Field of the Invention
The present disclosure relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present disclosure is directed to a source-biased Static Random Access Memory (SRAM) cell architecture for reducing leakage therein.
2. Description of Related Art
Static Random Access Memory (SRAM) devices comprising a plurality of memory cells are typically configured as an array of rows and columns, with one or more I/Os (i.e., x4, x8, x16, etc. configurations). Also, such memories may be provided in a multi-bank architecture for applications where high density, high speed and low power are required. Regardless of the architecture and type, each SRAM cell is operable to store a single bit of information. Access to this information is facilitated by activating all memory cells in a given row (by driving a wordline associated therewith) and outputting the data onto bitlines associated with a selected column for providing the stored data value to the selected output. Once the data is disposed on the bitlines, voltage levels on the bitlines begin to separate to opposite power supply rails (e.g., VDD and ground), and a sense amp is utilized to latch the logic levels sensed on the bitlines after they are separated by a predetermined voltage difference, typically 10% or less of VDD. Furthermore, the sense amp may be provided as a differential sense amp, with each of the memory cells driving both a data signal and a data-bar signal on the complementary bitlines (i.e., data lines) associated with each column. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value. Once a particular row and column are selected, the memory cell corresponding thereto is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level, typically VDD. The sense amp coupled to the two complementary bitlines senses the difference between the two bitlines once it exceeds a predetermined value and the sensed difference is indicated to the sense amp as the differing logic states of “0” and “1”.
As the transistor device sizes continue to decrease, e.g., 0.13μ or smaller, several issues begin to emerge with respect to the operation of SRAM cells, chiefly because at such dimensions the devices suffer from high values of leakage in the off state in standby mode. Essentially, these devices are no longer ideal switches; rather they are closer to sieves, having a non-negligible constant current flow path from drain to source or from drain/source to substrate even in the off state. The high leakage causes two major problems. First, because of the generation of large static current as leakage, there is increased static power consumption as a result. Second, which is more serious, is the issue of incorrect data reads from the SRAM cells. The accumulated leakage current from all the bitcells in a selected column is now comparable to the read current, thereby significantly eroding the bitline differential required for reliable sensing operations.
A technique for reducing standby leakage currents in a SRAM cell is disclosed in a recent article titled “16.7 fA/cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors” by Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe and Koichiro Ishibashi (in IEEE International Solid-State Circuits Conference, 2003, pages 302-303), where the source terminals of a plurality of SRAM cells on a single bitline column are coupled together for providing a biasing potential. Whereas such a scheme is seen to reduce total standby current, it does not improve the ratio of read current (IR) to cell leakage current (IL), however.